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» Synthesis of quantum logic circuits
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IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
14 years 1 months ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
13 years 11 months ago
A general state graph transformation framework for asynchronous synthesis
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekberg...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 1 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
DNA
2004
Springer
14 years 24 days ago
DNA Hybridization Catalysts and Catalyst Circuits
Practically all of life’s molecular processes, from chemical synthesis to replication, involve enzymes that carry out their functions through the catalysis of metastable fuels in...
Georg Seelig, Bernard Yurke, Erik Winfree
EVOW
2001
Springer
13 years 12 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...