18 search results - page 3 / 4 » Synthesis-for-scan and scan chain ordering |
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
EDBT
2006
ACM
14 years 7 months ago
2006
ACM
Abstract. Many different index structures have been proposed for spatial databases to support efficient query processing. However, most of these index structures suffer from an exp...
DFT
2005
IEEE
13 years 9 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
DFT
2002
IEEE
14 years 14 days ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...