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» Synthesizable High Level Hardware Descriptions
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RTAS
1997
IEEE
14 years 2 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
14 years 3 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...
DELTA
2010
IEEE
14 years 2 months ago
Algorithm Transformation for FPGA Implementation
— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Donald G. Bailey, Christopher T. Johnston
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 6 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
FCCM
2008
IEEE
177views VLSI» more  FCCM 2008»
14 years 4 months ago
Hardware Scripting in Gel
—Gel is a hardware description language that enables quick scripting of high level designs and can be easily extended to new design patterns. It is expression oriented and extrem...
Jonathan Bachrach, Dany Qumsiyeh, Mark Tobenkin