85 search results - page 9 / 17 » Synthesizable High Level Hardware Descriptions |
ICCAD
2001
IEEE
14 years 6 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
CASES
2007
ACM
14 years 1 months ago
2007
ACM
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
ASPDAC
2008
ACM
13 years 11 months ago
2008
ACM
—In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We a multiplier description language which abstracts from low-leve...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...
ARCS
2008
Springer
13 years 11 months ago
2008
Springer
Due to increasing complexity of modern real-time image processing applications, classical hardware development at register transfer level becomes more and more the bottleneck of te...