11 search results - page 1 / 3 » Synthesizing Iterative Functions into Delay-Insensitive Tree... |
ICCD
1997
IEEE
14 years 3 months ago
1997
IEEE
Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions ...
VLSI
2005
Springer
14 years 4 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
DELTA
2006
IEEE
14 years 2 months ago
2006
IEEE
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
MFCS
2000
Springer
14 years 2 months ago
2000
Springer
Abstract. We consider the iterates of bilinear functions over the semiring (max, +). Equivalently, our object of study can be viewed as recognizable tree series over the semiring (...
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
We present an efficient analog synthesis algorithm employing regression models of circuit matrices. Circuit matrix models achieve accurate and speedy synthesis of analog circuits...