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3DIC
2009
IEEE
120views Hardware» more  3DIC 2009»
14 years 2 months ago
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
—The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing Through Silicon Vias (TSV) for vertical connectivity is investigated with a cycle-a...
Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuw...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 11 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
GLOBECOM
2008
IEEE
13 years 9 months ago
Hierarchical Scanning Algorithm for Integrated Mobile and Nomadic Access Systems
—In next generation wireless networks, not only wide area cells to provide moderate data rate with full mobility but also local area cells to support high data rate with local mo...
Jung-Min Moon, Dong-Ho Cho
SAFECOMP
2004
Springer
14 years 1 months ago
Using Fuzzy Self-Organising Maps for Safety Critical Systems
This paper defines a type of constrained artificial neural network (ANN) that enables analytical certification arguments whilst retaining valuable performance characteristics. ...
Zeshan Kurd, Tim Kelly
JSAC
2006
120views more  JSAC 2006»
13 years 7 months ago
A Tutorial on Cross-Layer Optimization in Wireless Networks
This tutorial paper overviews recent developments in optimization-based approaches for resource allocation problems in wireless systems. We begin by overviewing important results i...
Xiaojun Lin, Ness B. Shroff, R. Srikant