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DSVIS
1998
Springer
14 years 2 days ago
Pragmatic Formal Design: A Case Study in Integrating Formal Methods into the HCI Development Cycle
Formal modelling, in interactive system design, has received considerably less real use than might have been hoped. Heavy weight formal methods can be expensive to use, with poor c...
Meurig Sage, Chris Johnson
JOT
2010
144views more  JOT 2010»
13 years 6 months ago
A Tool for Specifying and Validating Agents' Interaction Protocols: From Agent UML to Maude
To achieve the multi-agent systems’ goals, agents interact to exchange information, to cooperate and to coordinate their tasks. Interaction is generally recognized as an importa...
Farid Mokhati, Brahim Sahraoui, Soufiane Bouzaher,...
DATE
2004
IEEE
117views Hardware» more  DATE 2004»
13 years 11 months ago
Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks
We lay a foundation for modeling and validation of asynchronous designs in a multi-clock synchronous programming model. This allows us to study properties of globally asynchronous...
Mohammad Reza Mousavi, Paul Le Guernic, Jean-Pierr...
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 4 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna