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INFOVIS
2005
IEEE
15 years 10 months ago
Low-Level Components of Analytic Activity in Information Visualization
Existing system-level taxonomies of visualization tasks are geared more towards the design of particular representations than the facilitation of user analytic activity. We presen...
Robert A. Amar, James Eagan, John T. Stasko
TOMACS
1998
140views more  TOMACS 1998»
15 years 4 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...
DATE
2006
IEEE
126views Hardware» more  DATE 2006»
15 years 10 months ago
Communication and co-simulation infrastructure for heterogeneous system integration
With the increasing complexity and heterogeneity of embedded electronic systems, a unified design methodology at evels of abstraction becomes a necessity. Meanwhile, it is also i...
Guang Yang 0004, Xi Chen, Felice Balarin, Harry Hs...
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
15 years 9 months ago
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
FDL
2008
IEEE
15 years 6 months ago
Scenario-based Validation of Embedded Systems
This paper describes a scenario-based methodology em-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existi...
Angelo Gargantini, Elvinia Riccobene, Patrizia Sca...