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DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 11 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli
ERSA
2008
93views Hardware» more  ERSA 2008»
13 years 9 months ago
Multiparadigm Computing for Space-Based Synthetic Aperture Radar
Projected computational requirements for future space missions are outpacing technologies and trends in conventional embedded microprocessors. In order to meet the necessary levels...
Adam Jacobs, Grzegorz Cieslewski, Casey Reardon, A...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 9 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
ICCD
2004
IEEE
126views Hardware» more  ICCD 2004»
14 years 4 months ago
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...
Joshua L. Kihm, Daniel A. Connors
AGENTS
1998
Springer
13 years 12 months ago
Cognition and Affect: Architectures and Tools
Which agent architectures are capable of justifying descriptions in terms of the `higher level' mental concepts applicable to human beings? We propose a new kind of architect...
Aaron Sloman, Brian Logan