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search results - page 43 / 2467
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System Level Modelling for Hardware Software Systems
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ASPDAC
1998
ACM
67
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Hardware
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ASPDAC 1998
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Heterogeneous BISR-approach using System Level Synthesis Flexibility
14 years 1 months ago
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www.cs.ucla.edu
Inki Hong, Miodrag Potkonjak, Ramesh Karri
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29
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ICCD
1997
IEEE
91
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ICCD 1997
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Power Compiler: A Gate-Level Power Optimization and Synthesis System
14 years 23 days ago
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www.cs.berkeley.edu
Benjamin Chen, Ivailo Nedelchev
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25
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ISSS
2002
IEEE
111
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ISSS 2002
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System-Level Abstraction Semantics
14 years 2 months ago
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users.ece.utexas.edu
Daniel Gajski, Andreas Gerstlauer
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ICCD
1999
IEEE
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ICCD 1999
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Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study
14 years 1 months ago
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home.dei.polimi.it
William Fornaciari, Donatella Sciuto, Cristina Sil...
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DATE
2002
IEEE
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DATE 2002
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The Modelling of Embedded Systems Using HASoC
14 years 2 months ago
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www.dimap.ufrn.br
We present a design method (HASoC) for the lifecycle modelling of embedded systems that are targeted primarily, but not necessarily, at SoC implementations. The object-oriented de...
M. D. Edwards, P. N. Green
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