Sciweavers

5744 search results - page 3 / 1149
» System level design, a VHDL based approach
Sort
View
ITC
2003
IEEE
113views Hardware» more  ITC 2003»
14 years 4 months ago
Fault Injection for Verifying Testability at the VHDL Level
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allow...
S. R. Seward, Parag K. Lala
DSD
2007
IEEE
119views Hardware» more  DSD 2007»
14 years 5 months ago
Online Protocol Testing for FPGA Based Fault Tolerant Systems
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
Jiri Tobola, Zdenek Kotásek, Jan Korenek, T...
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
14 years 3 months ago
Generating VHDL models from natural language descriptions
This paper describes two approaches to the automatic generation of behavioral VHDL models from descriptions written in natural language. Both approaches are based on a modeling st...
Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik...
EURODAC
1995
IEEE
152views VHDL» more  EURODAC 1995»
14 years 2 months ago
Information model of a compound graph representation for system and architecture level design
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
Peter Conradi
DATE
2009
IEEE
150views Hardware» more  DATE 2009»
14 years 5 months ago
A co-design approach for embedded system modeling and code generation with UML and MARTE
—In this paper we propose a UML/MDA approach, called MoPCoM methodology, to design high quality real-time embedded systems. We have defined a set of rules to build UML models fo...
Jorgiano Vidal, Florent de Lamotte, Guy Gogniat, P...