169 search results - page 9 / 34 » System level memory optimization for hardware-software co-de... |
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—This paper presents a new two-levels page-based memory bus protection scheme. A trusted Operating System drives a hardware cryptographic unit and manages security contexts for e...
CLUSTER
2004
IEEE
13 years 11 months ago
2004
IEEE
Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop un...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of...
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...