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132
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ICCAD
2010
IEEE
119views Hardware» more  ICCAD 2010»
15 years 21 days ago
Symbolic system level reliability analysis
Abstract--More and more embedded systems provide a multitude of services, implemented by a large number of networked hardware components. In early design phases, dimensioning such ...
Michael Glaß, Martin Lukasiewycz, Felix Reim...
113
Voted
DATE
2006
IEEE
135views Hardware» more  DATE 2006»
15 years 8 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
15 years 9 months ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
98
Voted
ASPDAC
2005
ACM
125views Hardware» more  ASPDAC 2005»
15 years 8 months ago
A formalism for functionality preserving system level transformations
— With the rise in complexity of modern systems, designers are spending a significant time on at the system level of abstraction. This paper introduces Model Algebra, a formalis...
Samar Abdi, Daniel Gajski
137
Voted
ISQED
2010
IEEE
151views Hardware» more  ISQED 2010»
15 years 9 months ago
Leakage temperature dependency modeling in system level analysis
Abstract— As the semiconductor technology continues its marching toward the deep sub-micron domain, the strong relation between leakage current and temperature becomes critical i...
Huang Huang, Gang Quan, Jeffrey Fan