93 search results - page 4 / 19 » System-level memory modeling for bus-based memory architectu... |
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
ASPDAC
2007
ACM
14 years 16 days ago
2007
ACM
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
SBACPAD
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
SBACPAD
2008
IEEE
14 years 2 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
DATE
2004
IEEE
14 years 8 days ago
2004
IEEE
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...