9 search results - page 1 / 2 » System-level power estimation and optimization - challenges ... |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
CODES
2008
IEEE
13 years 7 months ago
2008
IEEE
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
CISS
2008
IEEE
14 years 2 months ago
2008
IEEE
—We consider a multiuser two-way relay network where multiple pairs of users communicate with their pre-assigned partners, using a common intermediate relay node, in a twophase c...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...