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» System-level power estimation and optimization
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ICCAD
2004
IEEE
118views Hardware» more  ICCAD 2004»
14 years 6 months ago
Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization
New embedded systems offer rich power management features in the form of multiple operational and non-operational power modes. While they offer mechanisms for better energy effic...
Jinfeng Liu, Pai H. Chou
DAC
2008
ACM
14 years 10 months ago
Low power passive equalizer optimization using tritonic step response
A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch,...
ICC
2008
IEEE
115views Communications» more  ICC 2008»
14 years 4 months ago
Joint Power Scheduling and Estimator Design for Sensor Networks Across Parallel Channels
—This paper addresses the joint estimator and power optimization problem for a sensor network whose mission is to estimate an unknown parameter. We assume a two-hop network where...
Lauren M. Huie, Xiang He, Aylin Yener
INFOCOM
2007
IEEE
14 years 4 months ago
QoS-Driven Power Allocation Over Parallel Fading Channels With Imperfect Channel Estimations in Wireless Networks
— We propose the quality-of-service (QoS) driven power allocation schemes for parallel fading channels when considering imperfect channel estimations. In particular, the parallel...
Jia Tang, Xi Zhang
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 2 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan