Sciweavers

392 search results - page 6 / 79
» System-level power estimation and optimization
Sort
View
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
14 years 10 months ago
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...
Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo
CODES
2004
IEEE
14 years 1 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
ASPDAC
2008
ACM
95views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Statistical power profile correlation for realistic thermal estimation
At system level, the on-chip temperature depends both on power density and the thermal coupling with the neighboring regions. The problem of finding the right set of input power pr...
Love Singhal, Sejong Oh, Eli Bozorgzadeh
DATE
1999
IEEE
118views Hardware» more  DATE 1999»
14 years 1 months ago
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Michael S. Hsiao
CODES
2004
IEEE
14 years 1 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...