82 search results - page 12 / 17 » SystemC transaction level models and RTL verification |
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
MICRO
2008
IEEE
13 years 7 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...