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» SystemJ: A GALS language for system level design
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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 1 months ago
Heterogeneous behavioral hierarchy for system level designs
Enhancing productivity for designing complex embedded systems requires system level design methodology and language support for capturing complex design in high level models. For ...
Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Ber...
CODES
2006
IEEE
14 years 1 months ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...
LCPC
2005
Springer
14 years 29 days ago
Software Thread Level Speculation for the Java Language and Virtual Machine Environment
Thread level speculation (TLS) has shown great promise as a strategy for fine to medium grain automatic parallelisation, and in a hardware context techniques to ensure correct TLS...
Christopher J. F. Pickett, Clark Verbrugge
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
14 years 1 months ago
Language-Based High Level Transaction Extraction on On-chip Buses
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chie...
FDL
2003
IEEE
14 years 23 days ago
Design and Power Analysis in SysteC of an I2C Bus Driver
The paper presents a methodology to integrate information on power consumption in a high level functional description of a System-on-chip. The power dissipated during the executio...
Marco Caldari, Massimo Conti, Paolo Crippa, Simone...