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» Systematic Integration Between Requirements and Architecture
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DAC
2010
ACM
13 years 12 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
ECBS
2007
IEEE
209views Hardware» more  ECBS 2007»
14 years 2 months ago
Aspect-Oriented Modeling of Ubiquitous Web Applications: The aspectWebML Approach
Ubiquitous web applications (UWA) are required to be customizable, meaning their services need to be adaptable towards the context of use, e.g., user, location, time, and device. ...
Andrea Schauerhuber, Manuel Wimmer, Wieland Schwin...
IJCNN
2007
IEEE
14 years 2 months ago
TRUST-TECH Based Neural Network Training
— Efficient Training in a neural network plays a vital role in deciding the network architecture and the accuracy of these classifiers. Most popular local training algorithms t...
Hsiao-Dong Chiang, Chandan K. Reddy
FDTC
2006
Springer
74views Cryptology» more  FDTC 2006»
13 years 11 months ago
Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection
Traditional hardware error detection methods based on linear codes make assumptions about the typical or expected errors and faults and concentrate the detection power towards the ...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
ISCAS
2006
IEEE
70views Hardware» more  ISCAS 2006»
14 years 2 months ago
A portable all-digital pulsewidth control loop for SOC applications
—A cell-based all-digital PWCL is presented in this paper. To improve design effort as well as facilitate systemlevel integration, the new design can be developed in hardware des...
Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu