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ECRTS
2009
IEEE
15 years 2 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
ERLANG
2007
ACM
15 years 8 months ago
Extended process registry for Erlang
The built-in process registry has proven to be an extremely useful feature of the Erlang language. It makes it easy to provide named services, which can be reached without knowing...
Ulf Wiger
SPAA
2006
ACM
15 years 10 months ago
Astronomical real-time streaming signal processing on a Blue Gene/L supercomputer
LOFAR is the first of a new generation of radio telescopes, that combines the signals from many thousands of simple, fixed antennas, rather than from expensive dishes. Its revol...
John W. Romein, P. Chris Broekema, Ellen van Meije...
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
15 years 9 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
ICASSP
2011
IEEE
14 years 8 months ago
Transmit and receive filters for MISO FBMC systems subjected to power constraints
Build upon the OFDM/OQAM scheme this paper addresses the design of linear transmit and receive filters. Aiming at enhancing the robustness against multipath fading, two novel tec...
Marius Caus, Ana I. Pérez-Neira