54 search results - page 5 / 11 » Teaching Hardware Description and Verification |
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
ISARCS
2010
13 years 9 months ago
2010
Methods of formal description and verification represent a viable way for achieving fundamentally bug-free software. However, in reality only a small subset of the existing operati...
FDL
2006
IEEE
13 years 11 months ago
2006
IEEE
In this work, an approach to the `verification-oriented' modeling of the analog parts' behavior of mixed-signal circuits is presented. Starting from a continuous-time, c...
FLAIRS
2008
13 years 9 months ago
2008
Storyboards are commonly known as rows of pictures, which exemplarily sketch scenes in performing arts. The rows specify the sequence of scenes. The scenes themselves are illustra...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an arithmetic bit level descrip...