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ASAP
2005
IEEE
87views Hardware» more  ASAP 2005»
15 years 9 months ago
Expression Synthesis in Process Networks generated by LAURA
The COMPAAN/LAURA [18] tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application a...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
ISSS
1999
IEEE
87views Hardware» more  ISSS 1999»
15 years 8 months ago
Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications
We present a new exploration and optimization method to select customized implementations for dynamic data sets, as encountered in telecom network, database and multimedia applica...
Chantal Ykman-Couvreur, J. Lambrecht, Diederik Ver...
ICON
2007
IEEE
15 years 10 months ago
A Cache Architecture for Counting Bloom Filters
— Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., u...
Mahmood Ahmadi, Stephan Wong
ICRA
2006
IEEE
77views Robotics» more  ICRA 2006»
15 years 10 months ago
Opening the Dialog: Robotics and the Internet
Abstract— Inter-component communication has received considerable attention by robotic software architects as various frameworks and toolkits have matured. While the resulting pl...
Anthony Cowley, Hwa-Chow Oliver Hsu, Camillo J. Ta...
ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
15 years 8 months ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...