3340 search results - page 156 / 668 » Teaching networking hardware |
137
click to vote
ASPDAC
2009
ACM
15 years 10 months ago
2009
ACM
— This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell e...
122
click to vote
DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
: This paper presents a domain decomposition (DD) technique for efficient simulation of large-scale linear circuits such as power distribution networks. Simulation results show th...
131
click to vote
ICCAD
1999
IEEE
15 years 8 months ago
1999
IEEE
Domino logic is a high-performance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. In this paper, the timi...
127
click to vote
DATE
2004
IEEE
15 years 8 months ago
2004
IEEE
This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case stu...
134
click to vote
TEI
2012
ACM
13 years 11 months ago
2012
ACM
This document presents a discussion about the Avaya S8300 and S8500 Media Server configured as a Local Survivable Processor (LSP). This discussion is intended to describe how the ...