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DATE
2007
IEEE
97views Hardware» more  DATE 2007»
15 years 10 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
ADHOCNOW
2005
Springer
15 years 10 months ago
An Intelligent Sensor Network for Oceanographic Data Acquisition
In this paper we describe the deployment of an offshore wireless sensor network and the lightweight intelligence that was integrated into the data acquisition and forwarding softwa...
Chris M. Roadknight, Antonio González, Laur...
ICCAD
2000
IEEE
113views Hardware» more  ICCAD 2000»
15 years 8 months ago
Don't Cares and Multi-Valued Logic Network Minimization
We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and sing...
Yunjian Jiang, Robert K. Brayton
ISCAS
1999
IEEE
114views Hardware» more  ISCAS 1999»
15 years 8 months ago
Channel equalization by feedforward neural networks
A signal su ers from nonlinear, linear, and additive distortion when transmitted through a channel. Linear equalizers are commonly used in receivers to compensate for linear chann...
Biao Lu, Brian L. Evans
ICCAD
1993
IEEE
81views Hardware» more  ICCAD 1993»
15 years 8 months ago
Inverter minimization in multi-level logic networks
In this paper, we look at the problem of inverter minimization in multi-level logic networks. The network is specified in terms of a set of base functions and the inversion opera...
Alok Jain, Randal E. Bryant