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DATE
2007
IEEE
106views Hardware» more  DATE 2007»
15 years 10 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
15 years 10 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 10 months ago
How OEMs and suppliers can face the network integration challenges
Systems integration is a major challenge in many industries. Systematic analysis of the complex integration effects, especially with respect to timing and performance, significant...
Kai Richter, Rolf Ernst
ISCA
2006
IEEE
120views Hardware» more  ISCA 2006»
15 years 10 months ago
Interconnection Networks for Scalable Quantum Computers
We show that the problem of communication in a quantum computer reduces to constructing reliable quantum channels by distributing high-fidelity EPR pairs. We develop analytical m...
Nemanja Isailovic, Yatish Patel, Mark Whitney, Joh...
ASYNC
2005
IEEE
142views Hardware» more  ASYNC 2005»
15 years 10 months ago
An Asynchronous Router for Multiple Service Levels Networks on Chip
Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementa...
Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Ey...