3340 search results - page 181 / 668 » Teaching networking hardware |
142
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
— In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is model...
173
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SIGMETRICS
2011
ACM
14 years 7 months ago
2011
ACM
Many network links in developing regions operate in the subpacket regime, an environment where the typical per-flow throughput is less than 1 packet per round-trip time. TCP and ...
136
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DAC
2005
ACM
16 years 5 months ago
2005
ACM
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
187
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
142
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ISSS
2002
IEEE
15 years 9 months ago
2002
IEEE
This paper presents a new technique for global energy optimization through coordinated functional partitioning and speed selection for embedded processors interconnected by a high...