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SIGMETRICS
1990
ACM
129views Hardware» more  SIGMETRICS 1990»
14 years 2 months ago
An Analytical Model of Multistage Interconnection Networks
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...
Darryl L. Willick, Derek L. Eager
ICRA
2008
IEEE
146views Robotics» more  ICRA 2008»
14 years 4 months ago
Visual servoing based on Gaussian mixture models
— In this paper we present a novel approach to robust visual servoing. This method removes the feature tracking step from a typical visual servoing algorithm. We do not need corr...
A. H. Abdul Hafez, Supreeth Achar, C. V. Jawahar
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
14 years 2 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
14 years 3 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
CODES
2004
IEEE
14 years 1 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...