684 search results - page 13 / 137 » Techniques for Accelerating a Grammar-Checker |
GLVLSI
2000
IEEE
14 years 2 months ago
2000
IEEE
Symbolic Model checking is a widely used technique in sequential verification. As the size of the OBDDs and also the computation time depends on the order of the input variables,...
ASPDAC
1998
ACM
14 years 2 months ago
1998
ACM
— The paper introduces a novel co-compiler and its “vertical” parallelization method, including a general model for co-operating host/accelerator platforms and a new parallel...
VISUALIZATION
2003
IEEE
14 years 3 months ago
2003
IEEE
We present a hardware-accelerated method for visualizing 3D flow fields. The method is based on insertion, advection, and decay of dye. To this aim, we extend the texture-based ...
TVLSI
2008
13 years 9 months ago
2008
Abstract--This paper presents a new set of techniques for hardware implementations of Secure Hash Algorithm (SHA) hash functions. These techniques consist mostly in operation resch...
ASPLOS
2012
ACM
12 years 5 months ago
2012
ACM
Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit thei...