66 search results - page 12 / 14 » Techniques for extracting instruction level parallelism on M... |
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
DAC
2005
ACM
14 years 7 months ago
2005
ACM
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
ISPDC
2010
IEEE
13 years 5 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
CASES
2005
ACM
13 years 8 months ago
2005
ACM
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...