66 search results - page 6 / 14 » Techniques for extracting instruction level parallelism on M... |
ISCAS
2005
IEEE
14 years 9 days ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
CODES
2003
IEEE
14 years 16 hour ago
2003
IEEE
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
CAMP
2005
IEEE
13 years 8 months ago
2005
IEEE
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
IPPS
2003
IEEE
14 years 3 hour ago
2003
IEEE
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...