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» Technology mapping for domino logic
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ICCAD
2006
IEEE
190views Hardware» more  ICCAD 2006»
14 years 4 months ago
Factor cuts
Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond...
Satrajit Chatterjee, Alan Mishchenko, Robert K. Br...
DAC
2002
ACM
14 years 8 months ago
River PLAs: a regular circuit structure
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
Fan Mo, Robert K. Brayton
FUIN
2010
116views more  FUIN 2010»
13 years 4 months ago
An Investigation of Multi-Agent Planning in CLP
This paper explores the use of Constraint Logic Programming (CLP) as a platform for experimenting with planning problems in the presence of multiple interacting agents. The paper ...
Agostino Dovier, Andrea Formisano, Enrico Pontelli
DAC
2006
ACM
14 years 8 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
13 years 11 months ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl