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» Temperature Variable Supply Voltage for Power Reduction
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FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
14 years 18 days ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...
ASPDAC
2007
ACM
136views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
Georges G. E. Gielen
DAC
2005
ACM
14 years 8 months ago
An efficient algorithm for statistical minimization of total power under timing yield constraints
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
Murari Mani, Anirudh Devgan, Michael Orshansky
ICCAD
2005
IEEE
87views Hardware» more  ICCAD 2005»
14 years 4 months ago
Statistical technology mapping for parametric yield
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky
CASES
2009
ACM
13 years 10 months ago
A case study of on-chip sensor network in multiprocessor system-on-chip
Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applic...
Yu Wang 0002, Jiang Xu, Shengxi Huang, Weichen Liu...