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» Test Generation and Fault Localization for Quantum Circuits
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ITC
2003
IEEE
134views Hardware» more  ITC 2003»
14 years 23 days ago
Effectiveness Improvement of ECR Tests
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
Wanli Jiang, Erik Peterson, Bob Robotka
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
14 years 1 months ago
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
Stephan Eggersglüß, Görschwin Fey,...
ATS
2003
IEEE
75views Hardware» more  ATS 2003»
14 years 24 days ago
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
VTS
1997
IEEE
86views Hardware» more  VTS 1997»
13 years 11 months ago
Methods to reduce test application time for accumulator-based self-test
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
Albrecht P. Stroele, Frank Mayer
VTS
1995
IEEE
100views Hardware» more  VTS 1995»
13 years 11 months ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey