1016 search results - page 16 / 204 » Test Generation for Designs with On-Chip Clock Generators |
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
IFIP
2001
Springer
14 years 2 days ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
EVOW
2001
Springer
14 years 3 days ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...