1016 search results - page 16 / 204 » Test Generation for Designs with On-Chip Clock Generators |
182
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VLSID
2001
IEEE
16 years 4 months ago
2001
IEEE
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
127
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GLVLSI
2006
IEEE
15 years 10 months ago
2006
IEEE
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
DAC
1999
ACM
16 years 4 months ago
1999
ACM
173
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IFIP
2001
Springer
15 years 8 months ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
152
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EVOW
2001
Springer
15 years 8 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...