1016 search results - page 19 / 204 » Test Generation for Designs with On-Chip Clock Generators |
DATE
1997
IEEE
13 years 12 months ago
1997
IEEE
A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IVconverter macro design....
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
RSP
2003
IEEE
14 years 27 days ago
2003
IEEE
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This paper describes the first application of the Genevieve test generation methodology. The Genevieve approach uses semi-formal techniques derived from "model-checking"...
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...