1016 search results - page 24 / 204 » Test Generation for Designs with On-Chip Clock Generators |
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
TSE
2010
13 years 2 months ago
2010
Genetic algorithms (GAs) have been applied previously to UML-driven, stress test requirements generation with the aim of increasing chances of discovering faults relating to networ...
VTS
1999
IEEE
13 years 12 months ago
1999
IEEE
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
SNPD
2003
13 years 9 months ago
2003
We present our experience in automatically deriving a detailed test case plan exclusively using the UML diagrams developed during the analysis and design phases. We consider in pa...