1016 search results - page 42 / 204 » Test Generation for Designs with On-Chip Clock Generators |
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
NETWORKING
2007
13 years 9 months ago
2007
We re-examine the two reasons for the conservative 1-second Minimum TCP-RTO to protect against spurious timeouts: i) the OS clock granularity and ii) the Delayed ACKs. We find tha...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
GECCO
2005
Springer
14 years 1 months ago
2005
Springer
Several general purpose benchmark generators are now available in the literature. They are convenient tools in dynamic continuous optimization as they can produce test instances w...