1016 search results - page 52 / 204 » Test Generation for Designs with On-Chip Clock Generators |
VTS
1999
IEEE
13 years 12 months ago
1999
IEEE
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
SIGCSE
2008
ACM
13 years 6 months ago
2008
ACM
We present the design and development of a Visual Learning Engine, a tool that can form the basis for interactive development of visually rich teaching and learning modules across...
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
WEA
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. A5/1 pseudo-random bit generator, known from GSM networks, potentially might be used for different purposes, such as secret hiding during cryptographic hardware testing, ...