1016 search results - page 6 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
ENGL
2008
13 years 7 months ago
2008
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
ISVLSI
2003
IEEE
14 years 26 days ago
2003
IEEE
Abstract— Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We propose a methodology for recovering m...
DDECS
2007
IEEE
13 years 9 months ago
2007
IEEE
— From an assumed property, which constrains the inputs of a design under test, we produce a RTL synthesizable design that generates compliant sequences of values for all the sig...