1016 search results - page 76 / 204 » Test Generation for Designs with On-Chip Clock Generators |
IASTEDSE
2004
13 years 9 months ago
2004
Pairwise coverage of factors affecting software has been proposed to screen for potential errors. Techniques to generate test suites for pairwise coverage are evaluated according ...
MTV
2005
IEEE
14 years 1 months ago
2005
IEEE
The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large p...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
PASTE
2004
ACM
14 years 1 months ago
2004
ACM
Test factoring creates fast, focused unit tests from slow systemwide tests; each new unit test exercises only a subset of the functionality exercised by the system tests. Augmenti...