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ATS
2002
IEEE
110views Hardware» more  ATS 2002»
14 years 10 days ago
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction
We propose a methodology that examines design modules and identifies appropriate vector justification and response propagation requirements for hierarchical test. Based on a cel...
Yiorgos Makris, Alex Orailoglu
DATE
2000
IEEE
87views Hardware» more  DATE 2000»
13 years 11 months ago
Test Synthesis for Mixed-Signal SOC Paths
Higher levels of integration, the need for test re-use, and the mixed-signal nature of today’s SOC’s necessitate hierarchical test generation and system level test composition...
Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 11 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
13 years 11 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
INFOCOM
2003
IEEE
14 years 19 days ago
Algorithms for Computing QoS Paths with Restoration
— There is a growing interest among service providers to offer new services with Quality of Service (QoS) guaranties that are also resilient to failures. Supporting QoS connectio...
Yigal Bejerano, Yuri Breitbart, Rajeev Rastogi, Al...