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» Test Resource Partitioning and Optimization for SOC Designs
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HPCA
2003
IEEE
14 years 9 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
IEEEPACT
2006
IEEE
14 years 2 months ago
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. I...
ICCSA
2005
Springer
14 years 2 months ago
Bringing Handhelds to the Grid Resourcefully: A Surrogate Middleware Approach
This paper presents the design of a middleware approach that aims at assisting handheld devices in accessing Grid services by wrapping the computational and resource intensive task...
Maria Riaz, Saad Liaquat Kiani, Anjum Shehzad, Sun...
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
13 years 9 days ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...
ASPDAC
2006
ACM
115views Hardware» more  ASPDAC 2006»
14 years 2 months ago
DraXRouter: global routing in X-Architecture with dynamic resource assignment
In recent years, the X-Architecture is introduced to obtain better performance for integrated circuit physical design. This paper reformulates the global routing problem in X-Archi...
Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hon...