145 search results - page 5 / 29 » Test Resource Partitioning and Optimization for SOC Designs |
ATS
2001
IEEE
14 years 7 days ago
2001
IEEE
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
TCAD
2002
13 years 8 months ago
2002
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...