Sciweavers

12 search results - page 1 / 3
» Test Scheduling and Scan-Chain Division under Power Constrai...
Sort
View
ITC
2003
IEEE
138views Hardware» more  ITC 2003»
14 years 1 months ago
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
Yannick Bonhomme, Patrick Girard, Loïs Guille...
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
14 years 5 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
ASPDAC
2006
ACM
90views Hardware» more  ASPDAC 2006»
14 years 2 months ago
A routability constrained scan chain ordering technique for test power reduction
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
X.-L. Huang, J.-L. Huang
ICCAD
2001
IEEE
113views Hardware» more  ICCAD 2001»
14 years 5 months ago
The Design and Optimization of SOC Test Solutions
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
Erik Larsson, Zebo Peng, Gunnar Carlsson