A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from t...
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad...
—Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q << k, a process termed space compaction. The ...
Krishnendu Chakrabarty, Brian T. Murray, John P. H...
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
For a space compactor, degradation of fault detection capability caused by the masking effects from unknown values is much more serious than that caused by error masking (i.e. ali...