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DFT
2003
IEEE
98views VLSI» more  DFT 2003»
14 years 29 days ago
Constrained ATPG for Broadside Transition Testing
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
Xiao Liu, Michael S. Hsiao
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
14 years 1 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
ISSTA
2006
ACM
14 years 1 months ago
Tool support for randomized unit testing
There are several problem areas that must be addressed when applying randomization to unit testing. As yet no general, fully automated solution that works for all units has been p...
James H. Andrews, Susmita Haldar, Yong Lei, Felix ...
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
14 years 29 days ago
Extending JTAG for Testing Signal Integrity in SoCs
As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically,...
Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nour...