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DATE
2000
IEEE
121views Hardware» more  DATE 2000»
14 years 2 days ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy
CONCUR
2006
Springer
13 years 11 months ago
Minimization, Learning, and Conformance Testing of Boolean Programs
Boolean programs with recursion are convenient abstractions of sequential imperative programs, and can be represented as recursive state machines (RSMs) or pushdown automata. Motiv...
Viraj Kumar, P. Madhusudan, Mahesh Viswanathan
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
14 years 29 days ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
ATS
2005
IEEE
132views Hardware» more  ATS 2005»
14 years 1 months ago
Concurrent Test Generation
We define a new type of test, called “concurrent test,” for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or m...
Vishwani D. Agrawal, Alok S. Doshi
DAC
2000
ACM
14 years 8 months ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy