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» Test generation in VLSI circuits for crosstalk noise
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DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 12 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
EH
2000
IEEE
123views Hardware» more  EH 2000»
14 years 1 days ago
The Test Vector Problem and Limitations to Evolving Digital Circuits
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digit...
Kosuke Imamura, James A. Foster, Axel W. Krings
GLVLSI
2005
IEEE
133views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Generating decision regions in analog measurement spaces
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
DATE
2005
IEEE
148views Hardware» more  DATE 2005»
14 years 1 months ago
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits
Multi-channel waveform monitoring technique enhances built-in test and diagnostic capability of mixed-signal VLSI circuits. An 8-channel prototype system incorporates adaptive sam...
Koichiro Noguchi, Makoto Nagata
DATE
1999
IEEE
102views Hardware» more  DATE 1999»
13 years 12 months ago
Minimal Length Diagnostic Tests for Analog Circuits using Test History
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...
Alfred V. Gomes, Abhijit Chatterjee