72 search results - page 7 / 15 » Test register insertion with minimum hardware cost |
ITC
2000
IEEE
13 years 11 months ago
2000
IEEE
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
ITC
2000
IEEE
13 years 12 months ago
2000
IEEE
We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for...
ITC
1994
IEEE
13 years 11 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM...